Why does atomic operation need exclusive cache access?Why do we need virtual functions in C++?atomic operation costC++11 introduced a standardized memory model. What does it mean? And how is it going to affect C++ programming?How do I achieve the theoretical maximum of 4 FLOPs per cycle?Why does changing 0.1f to 0 slow down performance by 10x?Atomic Compare Operator (No swap)Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviationsHow expensive are atomic operations?C++11: does atomic::compare_exchange_weak support none-primitive types?Why are mutexes different from atomic operations in that the former is OS level and the latter is processor level?
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Why does atomic operation need exclusive cache access?
Why do we need virtual functions in C++?atomic operation costC++11 introduced a standardized memory model. What does it mean? And how is it going to affect C++ programming?How do I achieve the theoretical maximum of 4 FLOPs per cycle?Why does changing 0.1f to 0 slow down performance by 10x?Atomic Compare Operator (No swap)Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviationsHow expensive are atomic operations?C++11: does atomic::compare_exchange_weak support none-primitive types?Why are mutexes different from atomic operations in that the former is OS level and the latter is processor level?
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In my understanding atomic operation (c++ atomic for example) first locks the cache line and then performs atomic operation. I have two questions: 1. if let's say atomic compare and swap is atomic operation itself in hardware why we need to lock cache line and 2. when cache line is locked how another cpu is waiting for it? does it use spin-lock style waiting?
thanks
c++ multithreading cpu atomic
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
add a comment |
In my understanding atomic operation (c++ atomic for example) first locks the cache line and then performs atomic operation. I have two questions: 1. if let's say atomic compare and swap is atomic operation itself in hardware why we need to lock cache line and 2. when cache line is locked how another cpu is waiting for it? does it use spin-lock style waiting?
thanks
c++ multithreading cpu atomic
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
2
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does providestd::atomicto give access to that H/W feature if available). Please, note thatstd::atomicmay fall back to other locking if H/W lock is not available for the locked type.std::atomic.
– Scheff
Mar 9 at 9:13
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03
add a comment |
In my understanding atomic operation (c++ atomic for example) first locks the cache line and then performs atomic operation. I have two questions: 1. if let's say atomic compare and swap is atomic operation itself in hardware why we need to lock cache line and 2. when cache line is locked how another cpu is waiting for it? does it use spin-lock style waiting?
thanks
c++ multithreading cpu atomic
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
In my understanding atomic operation (c++ atomic for example) first locks the cache line and then performs atomic operation. I have two questions: 1. if let's say atomic compare and swap is atomic operation itself in hardware why we need to lock cache line and 2. when cache line is locked how another cpu is waiting for it? does it use spin-lock style waiting?
thanks
c++ multithreading cpu atomic
c++ multithreading cpu atomic
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
asked Mar 9 at 9:03
shota silagadzeshota silagadze
185
185
2
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does providestd::atomicto give access to that H/W feature if available). Please, note thatstd::atomicmay fall back to other locking if H/W lock is not available for the locked type.std::atomic.
– Scheff
Mar 9 at 9:13
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03
add a comment |
2
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does providestd::atomicto give access to that H/W feature if available). Please, note thatstd::atomicmay fall back to other locking if H/W lock is not available for the locked type.std::atomic.
– Scheff
Mar 9 at 9:13
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03
2
2
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does provide
std::atomic to give access to that H/W feature if available). Please, note that std::atomic may fall back to other locking if H/W lock is not available for the locked type. std::atomic.– Scheff
Mar 9 at 9:13
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does provide
std::atomic to give access to that H/W feature if available). Please, note that std::atomic may fall back to other locking if H/W lock is not available for the locked type. std::atomic.– Scheff
Mar 9 at 9:13
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03
add a comment |
1 Answer
1
active
oldest
votes
First of all: It depends!
1.) If a system locks a cache line has nothing to do with c++. It is a question how a cache is organized and especially how assembler instructions acts with cache. That is a question for cpu architecture!
2.) How a compiler performs a atomic operation is implementation depended. Which assembler instructions will be generated to perform a atomic operation can vary from compiler to compiler and even on different versions.
3.) As I know, a full lock of a cache line is only the fall back solution if no "more clever" notification/synchronization of other cores accessing the same cache lines can be performed. But there are not only a single cache involved typically. Think of multi level cache architecture. Some caches are only visible to a single core! So there is a need of performing also more memory system operations as locking a line. You also have to move data from different cache levels also if multiple cores are involved!
4.) From the c++ perspective, a atomic operation is not only a single operation. What really will happen depends on memory ordering options for the atomic operation. As atomic operations often used for inter thread synchronization, a lot more things must be done for a single atomic RMW operation! To get an idea what all has to be done you should give https://www.cplusplusconcurrencyinaction.com/ a chance. It goes into the details of memory barriers and memory ordering.
5.) Locking a cache line ( if this really happens ) should not result in spin locks or other things on other cores as the access for the cache line itself took only some clock cycles. Depending on the architecture it simply "holds" the other core for some cycles. It may happen that the "sleeping" core can do in parallel other things in a different pipe. But hey, that is very hardware specific.
As already given as a comment: Take a look on https://fgiesen.wordpress.com/2014/08/18/atomics-and-contention/, it gives some hints what can happen with cache coherency and locking.
There is much more than locking under the hood. I believe your question scratches only on the surface!
For practical usage: Don't think about! Compiler vendors and cpu architects have done a very good job. You as a programmer should measure your code performance. From my perspective: No need to think about of what happens if cache lines are locked. You have to write good algorithms and think about good memory organization of your program data and less interrelationships between threads.
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
add a comment |
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First of all: It depends!
1.) If a system locks a cache line has nothing to do with c++. It is a question how a cache is organized and especially how assembler instructions acts with cache. That is a question for cpu architecture!
2.) How a compiler performs a atomic operation is implementation depended. Which assembler instructions will be generated to perform a atomic operation can vary from compiler to compiler and even on different versions.
3.) As I know, a full lock of a cache line is only the fall back solution if no "more clever" notification/synchronization of other cores accessing the same cache lines can be performed. But there are not only a single cache involved typically. Think of multi level cache architecture. Some caches are only visible to a single core! So there is a need of performing also more memory system operations as locking a line. You also have to move data from different cache levels also if multiple cores are involved!
4.) From the c++ perspective, a atomic operation is not only a single operation. What really will happen depends on memory ordering options for the atomic operation. As atomic operations often used for inter thread synchronization, a lot more things must be done for a single atomic RMW operation! To get an idea what all has to be done you should give https://www.cplusplusconcurrencyinaction.com/ a chance. It goes into the details of memory barriers and memory ordering.
5.) Locking a cache line ( if this really happens ) should not result in spin locks or other things on other cores as the access for the cache line itself took only some clock cycles. Depending on the architecture it simply "holds" the other core for some cycles. It may happen that the "sleeping" core can do in parallel other things in a different pipe. But hey, that is very hardware specific.
As already given as a comment: Take a look on https://fgiesen.wordpress.com/2014/08/18/atomics-and-contention/, it gives some hints what can happen with cache coherency and locking.
There is much more than locking under the hood. I believe your question scratches only on the surface!
For practical usage: Don't think about! Compiler vendors and cpu architects have done a very good job. You as a programmer should measure your code performance. From my perspective: No need to think about of what happens if cache lines are locked. You have to write good algorithms and think about good memory organization of your program data and less interrelationships between threads.
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
add a comment |
First of all: It depends!
1.) If a system locks a cache line has nothing to do with c++. It is a question how a cache is organized and especially how assembler instructions acts with cache. That is a question for cpu architecture!
2.) How a compiler performs a atomic operation is implementation depended. Which assembler instructions will be generated to perform a atomic operation can vary from compiler to compiler and even on different versions.
3.) As I know, a full lock of a cache line is only the fall back solution if no "more clever" notification/synchronization of other cores accessing the same cache lines can be performed. But there are not only a single cache involved typically. Think of multi level cache architecture. Some caches are only visible to a single core! So there is a need of performing also more memory system operations as locking a line. You also have to move data from different cache levels also if multiple cores are involved!
4.) From the c++ perspective, a atomic operation is not only a single operation. What really will happen depends on memory ordering options for the atomic operation. As atomic operations often used for inter thread synchronization, a lot more things must be done for a single atomic RMW operation! To get an idea what all has to be done you should give https://www.cplusplusconcurrencyinaction.com/ a chance. It goes into the details of memory barriers and memory ordering.
5.) Locking a cache line ( if this really happens ) should not result in spin locks or other things on other cores as the access for the cache line itself took only some clock cycles. Depending on the architecture it simply "holds" the other core for some cycles. It may happen that the "sleeping" core can do in parallel other things in a different pipe. But hey, that is very hardware specific.
As already given as a comment: Take a look on https://fgiesen.wordpress.com/2014/08/18/atomics-and-contention/, it gives some hints what can happen with cache coherency and locking.
There is much more than locking under the hood. I believe your question scratches only on the surface!
For practical usage: Don't think about! Compiler vendors and cpu architects have done a very good job. You as a programmer should measure your code performance. From my perspective: No need to think about of what happens if cache lines are locked. You have to write good algorithms and think about good memory organization of your program data and less interrelationships between threads.
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
add a comment |
First of all: It depends!
1.) If a system locks a cache line has nothing to do with c++. It is a question how a cache is organized and especially how assembler instructions acts with cache. That is a question for cpu architecture!
2.) How a compiler performs a atomic operation is implementation depended. Which assembler instructions will be generated to perform a atomic operation can vary from compiler to compiler and even on different versions.
3.) As I know, a full lock of a cache line is only the fall back solution if no "more clever" notification/synchronization of other cores accessing the same cache lines can be performed. But there are not only a single cache involved typically. Think of multi level cache architecture. Some caches are only visible to a single core! So there is a need of performing also more memory system operations as locking a line. You also have to move data from different cache levels also if multiple cores are involved!
4.) From the c++ perspective, a atomic operation is not only a single operation. What really will happen depends on memory ordering options for the atomic operation. As atomic operations often used for inter thread synchronization, a lot more things must be done for a single atomic RMW operation! To get an idea what all has to be done you should give https://www.cplusplusconcurrencyinaction.com/ a chance. It goes into the details of memory barriers and memory ordering.
5.) Locking a cache line ( if this really happens ) should not result in spin locks or other things on other cores as the access for the cache line itself took only some clock cycles. Depending on the architecture it simply "holds" the other core for some cycles. It may happen that the "sleeping" core can do in parallel other things in a different pipe. But hey, that is very hardware specific.
As already given as a comment: Take a look on https://fgiesen.wordpress.com/2014/08/18/atomics-and-contention/, it gives some hints what can happen with cache coherency and locking.
There is much more than locking under the hood. I believe your question scratches only on the surface!
For practical usage: Don't think about! Compiler vendors and cpu architects have done a very good job. You as a programmer should measure your code performance. From my perspective: No need to think about of what happens if cache lines are locked. You have to write good algorithms and think about good memory organization of your program data and less interrelationships between threads.
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
First of all: It depends!
1.) If a system locks a cache line has nothing to do with c++. It is a question how a cache is organized and especially how assembler instructions acts with cache. That is a question for cpu architecture!
2.) How a compiler performs a atomic operation is implementation depended. Which assembler instructions will be generated to perform a atomic operation can vary from compiler to compiler and even on different versions.
3.) As I know, a full lock of a cache line is only the fall back solution if no "more clever" notification/synchronization of other cores accessing the same cache lines can be performed. But there are not only a single cache involved typically. Think of multi level cache architecture. Some caches are only visible to a single core! So there is a need of performing also more memory system operations as locking a line. You also have to move data from different cache levels also if multiple cores are involved!
4.) From the c++ perspective, a atomic operation is not only a single operation. What really will happen depends on memory ordering options for the atomic operation. As atomic operations often used for inter thread synchronization, a lot more things must be done for a single atomic RMW operation! To get an idea what all has to be done you should give https://www.cplusplusconcurrencyinaction.com/ a chance. It goes into the details of memory barriers and memory ordering.
5.) Locking a cache line ( if this really happens ) should not result in spin locks or other things on other cores as the access for the cache line itself took only some clock cycles. Depending on the architecture it simply "holds" the other core for some cycles. It may happen that the "sleeping" core can do in parallel other things in a different pipe. But hey, that is very hardware specific.
As already given as a comment: Take a look on https://fgiesen.wordpress.com/2014/08/18/atomics-and-contention/, it gives some hints what can happen with cache coherency and locking.
There is much more than locking under the hood. I believe your question scratches only on the surface!
For practical usage: Don't think about! Compiler vendors and cpu architects have done a very good job. You as a programmer should measure your code performance. From my perspective: No need to think about of what happens if cache lines are locked. You have to write good algorithms and think about good memory organization of your program data and less interrelationships between threads.
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
edited Mar 9 at 9:35
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
answered Mar 9 at 9:30
KlausKlaus
11.3k12960
11.3k12960
add a comment |
add a comment |
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2
Have you read that one: fgiesen.wordpress.com/2014/08/18/atomics-and-contention
– Klaus
Mar 9 at 9:11
With multiple cores, the atomic change has to become effective for every core. As another core may have cached the same storage, it has to invalidate the storage to grant that it will "see" the change. IMHO, this is a H/W issue how in detail it is done. I'm not sure whether C++ is relevant for this (except that it does provide
std::atomicto give access to that H/W feature if available). Please, note thatstd::atomicmay fall back to other locking if H/W lock is not available for the locked type.std::atomic.– Scheff
Mar 9 at 9:13
That mental model is a bit too simplistic to really make headway, but processor manufacturers treat their memory controllers as a trade secret so it's not like you have many ways to make it more accurate. Every processor has a way to atomically update memory with a specific set of instructions. Which is all that std::atomic does, using those instructions. Other cores certainly can be stalled when such an update is in progress, you'd have to be a bit unlucky. Or write non-optimal code.
– Hans Passant
Mar 9 at 10:25
I just wanted to know why exclusive cache line access is needed when the atomic operation is atomic in itself for hardware ...
– shota silagadze
Mar 10 at 11:03